Cadence Design Systems Inc (NASDAQ:CDNS) Q3 2019 Earnings Conference Call - Final Transcript
Oct 21, 2019 • 05:00 pm ET
Our Intelligent System Design strategy, focus -- position us well to maximize the resulting opportunities through building out our portfolio, and providing more capabilities and value to our customers. The foundation of our strategy is the Design Excellence segment, which comprise of our core EDA and IP business. I will now provide some of the key quarterly highlights in this area.
A key element of our approach has been to closely collaborate with our ecosystem partners, and focus on market shaping customers. In Q3, we deepened our partnership with Samsung through our comprehensive agreement across our digital, custom, and verification product portfolio.
Early this year, we had reported a breakthrough wide-ranging win with a marquee US semiconductor company. I am particularly pleased that we augmented that partnership with our largest ever IP order that included our Tensilica processor family and our design IP portfolio, including ultra-high-speed SerDes.
At its recent open innovation platform event, TSMC recognized Cadence with four partners of the year awards, including an award for joint development of 6-nanometer design infrastructure. And one for joint delivery of cloud-based productivity solution. Our Cadence cloud portfolio has great momentum, with over 50 customers using our solution in the cloud. Cadence cloud-ready products in close collaboration with our cloud infrastructure and foundry partners are enabling our customers to realize meaningful scalability, performance and flexibility benefits from using the cloud.
Our CloudBurst model is used for hybrid cloud infrastructures, where customer want to augment their on-premise infrastructure with best capacity from the public cloud to address pick load. Continuing strong proliferation of our digital and signoff solutions, especially with market shaping customers at the most advanced nodes have driven share gains and double-digit year-to-date revenue growth.
In addition to numerous 7-nanometer tapeouts, there are more than 15 customer engagements at 5-nanometer and 3-nanometer using our digital flow. MediaTek has deployed our digital full flow in production for their 7-nanometer designs. At Mellanox, a leader in data connectivity solutions, Innovus replaced the incumbent solution for all of their production 7-nanometer designs. We also had a digital full flow competitive win for 7-nanometer design with a leading Japanese imaging company.
Uhnder used Cadence digital full flow, which is based on common engines and includes Genus, Innovus, Tempus and Pegasus to achieve the best quality of results and the fastest convergence of their highly innovative and completely integrated first digital automotive radar-on-chip.
Next, I will discuss highlights of our System Design and Verification solutions. Our Palladium Z1 emulator, and the recently introduced Protium X1 FPGA-based prototyping platform now provide a comprehensive solution across IP and SoC verification, hardware/software regressions, and earlier software development. Growing system design complexity and the high cost of failure continues to drive strong demand for our Palladium Z1. In Q3, the Z1 added eight new customers and had key -- and had eight key expansions.
Rounding off our hardware family is the Protium X1, which is a perfect complement to our Palladium Z1. I'm excited by the strong customer